1. Field of the Invention
The present invention relates generally to the fabrication of semiconductor dice. More particularly, the present invention pertains to methods and apparatus for redistributing bond pads on semiconductor dice to more widely pitched locations to facilitate formation of semiconductor die assemblies.
2. State of the Art
As is well known, the manufacture of semiconductor devices involves many process steps. A large number of like semiconductor devices may be fabricated on a thin wafer or other bulk substrate of semiconductive material such as silicon. Each semiconductor device comprises a chip or die of semiconductor material onto which are fabricated various electronic components such as transistors, inductors, resistors and capacitors, all operably connected to form a useful device. The wafer is then subdivided to form the discrete semiconductor devices, also known as integrated circuits (ICs). The semiconductor devices may be protectively packaged either prior to or following a singulation step, wherein the wafer is severed into individual semiconductor devices. While integrated packages may be formed of two or more chips, the integration of multiple functional circuits on single chips has also become common, leading to chips with a large number of input/output (I/O) terminals for signal transmission, power supply, ground (or bias), and testing. There has been a continuing effort in the industry to enhance the functional density of semiconductor devices while simultaneously decreasing their size. Densification in chip fabrication has many advantages, including overall reduction in cost, reduction in package volume, and enhanced electrical efficiency due to shorter signal transmission paths. Moreover, increased miniaturization has enabled the formation of complex integrated circuits on a single chip or die, such as a so-called “computer on a chip.”
In general, the circuits on a chip or die terminate in conductive bond pads arrayed on the die's active surface, typically in one or more rows about the die periphery or across a central portion of the die. These bond pads are generally formed of aluminum or an aluminum alloy and are designed to be conductively connected to terminals of a carrier substrate such as an interposer or circuit board, the pattern of terminals on which may not correspond to the locations of the corresponding bond pads on the die. In addition, the lateral bond pad-to-bond pad separation (pitch) may be too close for satisfactory direct attachment to a substrate. Thus, if the conductive connection to carrier substrate terminals is to be at least in part by wire bonding, as in a dense wafer-level chip-scale package, it is difficult to achieve the desired connection without crossing of wires, undue closeness of wires, or an overly steep bonding angle, all of which may lead to a higher frequency of shorting, such as may be induced by wire sweep. Currently proposed packages have even greater numbers of bond pads packed into smaller spaces, i.e., with finer pitch.
Where a conventional package is intended to be attached in flip-chip configuration to conductive areas of an interposer or other substrate, i.e., by direct attachment with solder bumps, a redistribution layer (RDL) is currently added to the package. A conventional wafer-level semiconductor package 10 with a single RDL 20 is depicted in Prior Art FIG. 1. The package 10 comprises a semiconductor die 12 with an active surface 18 and a backside 28. The package 10 includes a plurality of conductive die bond pads 14 on the active surface 18, typically either in a peripheral arrangement or along a generally central axis. In this prior art package, a die passivation layer 16 covers the active surface 18 between the die bond pads 14 to protect and electrically insulate the active surface 18. A conventional RDL 20 comprises a metallization layer formed on the die passivation layer 16 or on one or more additional layers 26A, 26B . . . 26N of passivating material. The metallization layer is typically applied by a thin film deposition process which requires photolithography and etching to define the traces of RDL 20 therefrom. Various methods may be used for forming the under-bump metallization (UBM) 22 to which the redistribution layer (RDL) 20 is joined. Typically, a UBM 22 consists of at least an adhesion/fusion barrier layer and a wetting layer (and often an intermediate layer), in order to form a pad structure which adheres well to traces of RDL 20 and to which a solder material will be attracted, or “wet,” when heated to a molten state during formation of a solder ball or bump 24. The package 10 may be inverted atop a substrate such as an interposer (not shown) and the solder balls or bumps 24 joined to conductive areas in the form of terminal pads thereon. In a complex high-pitch ball array package, two or three redistribution metallization layers may be used, with intervening passivation layers separating the metallization layers. As a result, multiple steps of passivation deposition, etching, metallization deposition and etching are required.
Variations and improvements of the basic redistribution metallization layer are described in the following references:
U.S. Pat. No. 5,554,940 of Hubacher describes a redistribution layer which, in addition to bump pads, also includes separate test pads which may be contacted with cantilever probe needles. Each test pad is situated near a respective bond pad so that the same (or similar) probe card apparatus and cantilever needles may be used to test the semiconductor device, either on the bond pads (for a wire-bonded device) or on the test pads (for a bumped device).
In U.S. Pat. No. 6,536,653 of Wang et al., a method for bumping and bonding semiconductor packages is disclosed.
U.S. Pat. No. 6,204,562 of Ho et al. reveals a multichip module (MCM) for flip-chip attachment. The package is formed of a plurality of wafer-level chip-scale dice, wherein the larger die uses a bump pad redistribution layer for joining the dice in a flip-chip manner.
In U.S. Pat. No. 6,197,613 of Kung et al., a first bump pad redistribution layer is connected to a second redistribution layer at a different level by a via plug passing through an applied insulating layer.
In U.S. Pat. No. 6,372,619 of Huang et al., a redistribution layer is connected to elevated bump pads by vias through an insulating layer.
U.S. Pat. No. 6,433,427 of Wu et al. teaches a wafer-level package having a redistribution layer in which the redistributed bump pads are underlain by two stress-buffer layers.
U.S. Pat. No. 6,277,669 of Kung et al. describes a method for making a pad redistribution layer on a wafer-level package, wherein the distributed bump pads are underlain by an elastomeric material.
U.S. Pat. No. 6,043,109 of Yang et al. describes a method for making a wafer-level two-die package utilizing a redistribution layer on the smaller of the dice and connecting the redistribution layer to the larger die by wire bonding.
In each of the above references, one or more redistribution layers are used, typically requiring multiple deposition and etching steps. Expensive masks and reticles are required. Under-bump metallization (UBM) will also be required at the redistributed bond pad locations, adding to the overall cost. Thus, the current methods of forming RDLs require many processing steps and are time consuming and expensive. In addition, for each change in die size, for example, die “shrinks,” a heavy capital investment will be incurred. The actual extent of production costs has not been fully delineated because conventional RDL technology is relatively new and not yet fully developed. Further, there is substantial incompatibility between terminal pad pitch of many carrier substrates, such as module boards used to fabricate multichip modules, and solder ball pitch of dice employing conventional RDL technology. For example, terminal pad pitch may be constrained to about 0.5 mm, whereas solder ball pitch may be significantly finer, for example, about 0.1 to 0.2 mm.
In the manufacture of packages using redistribution metallization, the dice are typically packaged prior to Known Good Die (KGD) testing. Thus, it is important to achieve a very high yield in order to reduce production costs. However, in the current state of the art, the yield is known to be unacceptably low.
It would be desirable to provide a chip-scale semiconductor package with increased pitch, increased yield, fewer packaging steps, and at reduced cost.
It would also be desirable to provide a chip-scale semiconductor package which may be attached to a carrier substrate either by wire bonding or by flip-chip attachment.
It would be further desirable to provide a chip-scale semiconductor package with improved redistribution of bond pads.
It would be still further desirable to provide an improved pad redistribution method useful for chip-scale flip-chip semiconductor packages having die bond pads either along the die periphery or along a central axis across the die.